Meet our best mentors

Vaibhava Mishra

Mentor @ ASIC Design Layout and FPGA

Vaibhava Mishra has over 12 years of technical and management experience in the semiconductor (FPGA) industry as Application Engineer. He has worked on Xilinx and Altera platforms. He holds B-Tech in electronics and communication from Northern India Engineering College, Lucknow. He has also done Advanced Post Graduation diploma in VLSI designs from VEDANT, Mohali (Chandigarh).

Apurv K Singh

Mentor @ ASIC Design Layout and FPGA

Apurv K Singh has experience of over 15 years in design & development of hardware systems, FPGA and Telecom products. He holds M.Tech degree from IIT Delhi in Electronics. He has extensively worked on FPGA development meant for high end systems particularly related to telecom & networking and has wide experience working on Xilinx and Mentor Platforms.

Raj Kumar

Mentor @ Embedded

Raj kumar has 12 years of experience in embedded design and development on 8/16/32 bit platform  and Architecture. 10 years on c and 2 years development using c, win32 c. Experience include device driver deployment on Linux, kernel level programming on Linux, cross tool chain for board, also worked on wince 5.0 for stream device driver. Worked on Zigbee stack in wireless domain for 2.4 GHz as ism band, Worked on contiki OS (Linux OS ) cross tool chain and application for CC2530 SOC from TI, besides above worked various microcontroller with real time OS like uCOS-ii, rtx tiny, wince 5.0 with platform builder, measuring instrument for weight, voltage, current and power Firearm based system. During this long duration of experience he had handle project independently as well as in team. His role also in writing software as well as firmware part. Handling Embedded SW & HW and Management @ PINE

Mentor 2

Professional with approx. 11  years of experience in Semiconductor industry. Experience in layout (SOC, analog and I/O) in various CMOS technologies (16/14FinFet, cmos32lp-28lp, cmos45fg-40lp/fg-45SOI, cmos65-55lp/fg, cmos90-90rf, cmos180,  IMG110, IMG140, IMG175, IMG220 etc)Experience in chip top integration e.g.  chips (approx. 20 WB pads and 5mm square --Virtuoso out). Experience in full chip and Analog layout for USB3.0/2.0, MIPI D-PHY IP Core, HDMI Tx, CDR Tx/Rx, LDO, PLL etc. Expertise in handling reliability checks for VLSI layouts, EM/IR drop/Antenna/DFM/ESD/LatchUp issues. Mentor and Guide Junior members of the team And also responsible for analog layout training/reviews/automation etc. Basic knowledge of Virtuoso Skill Scripting.  Tools  : SOC Encounter,  Voltus, Redhalk, Virtuoso (XL) layout editor (icfb/OA),Virtuoso skill, Laker, IC-Station, Calibre (DRC/DFM/LVS/MRC), Star-RCXT Operating system      :        Solaris, Linux, windows. Handling Full Custom Layout @ PINE.

Mentor 1

Automation Engineer having experience of 12+ years working in several chip design companies. Well versed experience working on EDA flow and methodology in Memory, RF and Analog space. Rich experience on tool knowledge (Cadence, Synopsys, Mentor), scripting, licensing, PDK and various other aspects of EDA. Handling Scripting @ PINE

Mentor 3

M.Tech in Vlsi design IIT Kharagpur. Worked on the analog front end design for motion and pressure sensor. Having experience of Working on voltage regulator, DSI PSI communication protocol, basic analog block like opamp, comparator bias generator circuits and executed full SOC AMS simulation. Hands on experience on silicon debug. Handling Analog @ PINE.

Mentor 4

Industry Experience 12 years in the field of VLSI Design Digital Domain. Expertise in designing of circuit, Timing closure of SOC, Characterization of Standard cell and IOcell, RTL modeling. Handling Digital @ PINE

Mentor 5

Industry experience of 3 years of Verification experience in different companies as R & D engineer. He has worked on SoC Verification, IP Verification, Subsystem Verification, Verification IP Development on different tools like VCS, ncsim and Questa. He has also worked on different protocols like Ethernet ,AXI, AHB etc. He holds M.Tech degree in VLSI design from Nirma University. Handling C,C++, Verilog and System Verilog and UVM @ PINE.

Mentor 6

M.Tech in Vlsi design from IIT BHU. Worked on the analog design IP’s like Oscillators, Band gap Reference, High Speed Clock dividers, Power on reset circuit, switch capacitor circuit on latest technology like 28nm, 16nm finfet. He is also having of Full Custom Layout and Design flow. Handling Analog @ PINE.

Mentor 7

Industry expereince of 6 years of experience in FPGA DSP. He having vast working experience on ANALOG AND DIGITAL COMMUNICATION, SIGNALS AND SYSTEM, DIGITAL ELECTRONICS, WIRELESS COMMUNICATION, AUTOMATIC,CONTROL SYSTEM, DIGITAL SIGNAL PROCESSING. He has achieve physical application of AM-SSB, FM, AM-DSB, Digital AGC and Squelch (Module), DUC(Digital Up Convertor) and DDC (Digital Down Convertor), Adaptive Linear Equalizer based on LMS Technique, Low Data Rate waveform (up to 64 Kbps), High Data Rate Waveform ( up to 2 & 6 Mbps), Phase Offset and frequency Offset/Doppler Correction Techniques, Symbol Timing Recovery, Phase Ambiguity Resolution for PSK Modulated Signals, SNR Estimation Method for TCC Decoder. Also have a good knowledge of ADCs and DACs, LTE, MIMO, good signal processing concepts required for modeling in Xilinx system generator, simulation activities on Simulink for various channel models for high data rate modem in V/UHF environment. LTE physical layer based development is also in design phase. Moreover, Waveforms/Modules are approved by Dr. Surender Prasad, IIT DELHI. Handling DSP FPGA @ PINE

Mentor 8

Industry Experience of 2 years in the field of FPGA Embedded Software and Hardware design. Has had worked Xilinx based ZYNQ platform and implemented Analog Device SOC in FPGA as well ZYNQ interface for existing telecom based product. Handling FPGA Embedded at PINE.

Mentor 9

Industry experience of 2 year experience in VLSI design and STA domain. He Having good exposure of EDA standard PnR and STA tools. Expertise in Floorplanning, placement, cts, routing, congestion removal, LVS and DRC fix, LEC checks etc. Experience in improving many timing failure. designs. Hands on knowledge of all timing concept. Working for enhancement of new technology and features addition in STA tool. Handling Coding, Synthesis and Timing @ PINE

Mentor 10

A technology driven professional with 7+ years of experience in System Software and Application Software Development. Adept in all phases of software & hardware development, product development and production life cycle. Hands on experience in System development and unit testing of Embedded applications. In-depth understanding of System Development Life Cycle including study of specifications, requirement gathering, designing, integration, testing, documentation and support. An effective communicator with strong interpersonal, team management, relationship management, coordination and analytical skills. Handling Embedded Design @ PINE

Mentor 11

He is having two year working experience  Board Hardware design . He having exposure on Tool used for board design like ORCAD, KICAD(open source), Eagle, High speed routing on Orcad and designing up to 6 layer of board. Handling PCB Design @ PINE.