Physical Design – Advance VLSI Design

VLSI Physical Design – Advance VLSI Design Course

Project Oriented Six Month Weekend Training Program on Physical Design – Advance VLSI Design

Objective: : To Prepare dedicate team of hardware & software engineer who are capable to take up project into VLSI industries in fresher profile.

  • Duration: 6 Months
  • Batch Commence: 6 Jan. 2018
  • Training Batch Size: 25 Students
  • Placement Assistance: YES

Eligibility: 2017 Pass out B.E / B.Tech / M.Tech from EC, EEE, CS can Join this.

Selection Procedure: Written test based on Engineering Subject & Personal Interview

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  • Understanding of Various Data Types
  • Understanding of Various Input And Output Files
  • Understanding of Liberty File Format
  • Understanding Various Basic Components Such As Flip Flop, Latch Etc.
  • Die Size Estimation
  • Difference Between Full Chip And Block
  • Floorplan
  • Placement
  • Clock Tree Synthesis
  • Routing
  • Physical Verification Checks (DRC/LVS/ERC/ANTENNA/XOR)
  • Static Timing Analysis
  • DFM
  • DFT for PD
  • Extraction (Star-RC)
  • Engineering Change Order (ECO)

Placement 2016-2017

Mridalini Mishra

Cadence, Noida

Alok Nigam

Synopsys, Noida

Raman Raj Srivastava

Eigen Technologies

Akshay Nayar


Mridul Verma


Garvit Goyal


Chirag Gupta


Vasvi Gupta


Ashish Chaurasia

Sankalp Semiconductor

Ram Niwas

SI2 Chip

Interested Candidates, Please Register Yourself by Google Form Before 25th Dec 2017
Career Opportunities After Completion of Engineering
90 Trainees Placed from 2014 till Date In Core

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